A Cryogenic 8-Bit 32 MS/s SAR ADC Operating down to 4.2 K

This paper presents a cryogenic 8-bit 32 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) which operates down to 4.2 K. work uses modified liquid helium temperature (LHT) SMIC 0.18 μm CMOS technology support the post-layout simulation. The proposed architecture adopts an offset-promoted dynamic comparator, waveform shaping circuit and true single-phase clock (TSPC) based sar logic achieve high realizing frequency low power dissipation. At 1.8-V supply, 1.7 V input amplitude sampling frequency, ADC achieves consumption of 2.4 mW signal-to-noise distortion ratio (SNDR) 47.7 dB, obtaining figure merit (FOM) 378 fJ/conversion-step. layout area is about 0.253 mm2.